This invention relates to a communication apparatus and, in particular, relates to a communication apparatus for processing packets.
The traffic volume in network systems is swelling because of prevalence of digitalization of television contents or web video distribution services in recent years. As a result, the demand for communication lines having a capacity of over 100 Gbps is increasing.
The operating frequency of a logic device in a packet communication apparatus is elevated with the increase in traffic volume; however, the operating frequency of an FPGA (Field-Programmable Gate Array), which is an example of a logic device, is limited to about 300 MHz at most. For this reason, to install a 100-Gbps line with an FPGA, the FPGA is required to process packets in the order of 2 clks per packet.
To implement a packet management function such as a bandwidth control function or a statistical counting function in a logic device, the logic device sorts the information on packets by flow to store it in an information storage medium (hereinafter, referred to as a table) and at every arrival of a packet, updates a value in the table specific to the flow which is associated with the incoming packet.
For example, to perform the bandwidth control function, the logic device manages the bandwidth consumed by each flow in a table. Specifically, the logic device reads a bandwidth allocated to a flow (allocated bandwidth) and a bandwidth consumed by the flow (consumed bandwidth) from the table (a. table RD) at every arrival of a packet, updates the consumed bandwidth and compares the update result with the allocated bandwidth (b. data computation), and writes the update result of the consumed bandwidth to the table (c. table WR).
Hereinafter, updating the table with information about a packet, like the foregoing a. to c., is referred to as table updating.
A common method of updating a table is that a logic device updates the table on a packet-by-packet basis at every arrival of a packet (sequential processing method). In the sequential processing method, the logic device usually takes a certain time (for example, about 10 clks) in the table updating for one packet.
In the field of this invention, there is a background art disclosed in JP 2000-358066 A. The method according to JP 2000-358066 A checks, for each inbound packet, whether another packet from the same source is pending at an individual processing element, and if the result of the checking is positive, forwards the inbound packet to the individual processing element. In other words, JP 2000-358066 A provides a parallel processing technique that a plurality of parallel processing modules process packets of a plurality of flows.